1. Field of the Invention
Generally, the present disclosure relates to the field of fabricating microstructure devices, and, more particularly, to techniques for enhancing product yield by reducing the defect rate at several process stages during the formation of complex microstructures, such as integrated circuits and the like.
2. Description of the Related Art
Today's global market forces manufacturers of mass products to offer high quality products at a low price. It is thus important to improve yield and process efficiency to minimize production costs. This holds especially true in the field of fabricating microstructures having a complex configuration, such as advanced integrated circuits, since here it is essential to combine cutting edge technology with mass production techniques. It is, therefore, the goal of manufacturers of microstructures to reduce the consumption of raw materials and consumables while at the same time improve process tool utilization. The latter aspect is especially important, since in modern semiconductor facilities, equipment is required which is extremely cost intensive and represents the dominant part of the total production costs. Consequently, high tool utilization in combination with a high product yield, i.e., with a high ratio of good devices and faulty devices, results in increased profitability.
Complex microstructures, such as integrated circuits, are typically manufactured in automated or semi-automated facilities, thereby passing through a large number of process and metrology steps to complete the device. The number and the type of process steps and metrology steps a semiconductor device has to go through depends on the specifics of the device to be fabricated. For example, a usual process flow for an integrated circuit, which may be considered as a representative of a complex microstructure, may include a plurality of photolithography steps to image a circuit pattern for a specific device layer into a resist layer, which is subsequently patterned to form a resist mask used in further processes for forming device features in the device layer under consideration by, for example, etch, implant, deposition, polish processes and the like. Thus, layer after layer, a plurality of process steps are performed based on a specific lithographic mask set for the various layers of the specified device. For instance, a sophisticated CPU requires several hundred process steps, each of which has to be carried out within specified process margins so as to fulfill the specifications for the device under consideration. Since many of these processes are very critical, a plurality of metrology steps have to be performed to efficiently control the process flow. Typical metrology processes may include the measurement of layer thickness, the determination of dimensions of critical features, such as the gate length of transistors, the measurement of dopant profiles, the number, the size and the type of defects, and finally the electrical characteristics, which may represent the contribution of a plurality of process stages and which may finally decide whether a device is an operational device or a faulty device.
In a semiconductor facility, a plurality of different product types are usually manufactured at the same time, such as memory chips of different design and storage capacity, CPUs of different design and operating speed, and the like, wherein the number of different product types may even reach one hundred and more in production lines for manufacturing ASICs (application specific ICs). Since each of the different product types may require a specific process flow, different mask sets for the lithography, specific settings in the various process tools, such as deposition tools, etch tools, implantation tools, chemical mechanical polishing (CMP) tools, metrology tools and the like, may be necessary. Consequently, the process flow in the facility may be very complex, since many re-entrant processes, i.e., a repeated use of the same process tools at different manufacturing stages of a specific type of product, and many predictable and non-predictable events may occur during the manufacturing processes and the various metrology processes, resulting in respective waiting times of substrates at specific manufacturing stages. In some cases, extended idle time periods may have a significant influence on the status of the intermediate products, thereby contributing to a reduced product reliability and/or a reduced yield. For instance, in sophisticated semiconductor devices, frequently highly conductive metals, such as copper and the like, may be used in the wiring levels of the device, which are subject to increased corrosion even when stored in a controlled ambient. As previously noted, electrical tests are typically performed at specific manufacturing stages, in particular prior to dicing the substrates into individual chips, wherein more or less extended metal-containing surfaces may be exposed. Since electrical tests for each individual chip are usually time consuming and possibly only a limited test capacity may be available, a relatively long exposure of the metal surfaces of respective test and device pads may occur, thereby resulting in a significant modification of the exposed surfaces, such as corrosion, discoloration and the like. Moreover, the electrical test process itself may create significant particle contamination due to the operation of the probe electrodes and the like in close proximity to the substrates. In other processes, such as CMP processes, a plurality of defects may also be created, such as particles, which may deposit on exposed wafer surfaces, tool surfaces and the like, thereby additionally contributing to an increased defect rate, which may finally reduce the overall production yield.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.